1. Field of the Invention
The present invention relates to data processing.
2. Background Information
In a real-time processing environment, a processor may be expected to complete one or more computational tasks no later than a certain time. For example, the processor may be expected to provide one or more computational results within a specified time period. Whether the processor executes the tasks sufficiently quickly to satisfy the time constraint may depend on factors such as the complexity of the tasks, the nature of the input, the design of the processor, and the rate at which the processor is clocked.
Some of these factors may be difficult or impossible to control at run time. For example, the design (e.g. the instruction set architecture) of the processor may be fixed during its manufacture. Other factors may be altered during system design. With other factors remaining constant, for example, the execution speed of a processor may be increased by increasing its clock frequency (within the physical limits of the particular processor).
One approach to real-time system planning is to determine (or estimate) the worst-case processing load and set the clock frequency accordingly. In some applications, however, it may be desirable to clock a processor at a rate that is less than would be required to satisfy the worst-case load. For example, power consumption is also related to clock frequency. Especially in process technologies such as CMOS (complementary metal-oxide-semiconductor), power dissipation increases strongly with clock frequency. In portable applications, the commercial viability of a particular design may depend on battery life, and selecting a worst-case rate for the processor clock may result in an unacceptable waste of available power.
In some applications, it may be desirable to use a clock source that is already available. In a portable wireless device, for example, one or more clock sources (e.g. oscillators) may already be present to generate signals used for radio-frequency operations such as modulation or demodulation. Using an available clock source may conserve chip area (e.g. by avoiding chip area consumption by an additional clock source and distribution network) and may also avoid or reduce the potential for interference between different clock sources.
Unfortunately, a clock source whose frequency is selected to reduce power consumption, or a clock source that is already available, may not provide adequate execution speed to satisfy the worst-case processing requirements. An overload condition occurs when a processing task does not complete when expected. In some applications, a resulting unavailability of data or conflict between tasks may cause an undesirable degradation of performance. It is desirable to reduce or avoid degradation in a system where an overload condition may occur.
In other applications, unavailability of data or conflict between tasks may lead to an invalid or undefined operation or may otherwise cause a system to become unstable. It is desirable to avoid unstable operation in a system where an overload condition may occur.